1. Field of the Invention
The present invention relates to clock driven electrical systems and, more particularly, to electrical circuits for use in reducing power consumption of clock driven electrical systems.
2. History of the Prior Art
The minimization of power consumption is an important objective of many electrical circuit designs. Reduced power consumption is generally desired for a number of reasons, one of which in the case of battery powered circuits, is to extend the life of the battery. In battery powered circuits, a reduction in power consumption of an electrical device is generally expected to extend the life of the battery powering that circuit. An extended battery life is useful in many applications. In the case of a battery powered circuit in a cordless telephone, for example, an extended battery life allows for longer idle time, that is, the period of time between uses.
As is generally known in the electrical art, the power consumption of an electrical system composed of a number of functional blocks may be controlled by use of a number of different power modes, some modes allowing certain functional blocks in the system to be disabled. These power modes may include a fully active mode wherein all functional blocks are active, partly active modes wherein only the functional blocks that are necessary for minimal operation are enabled, and a power-down mode wherein all functional blocks are disabled except those required to recognize key events that will force the system back into an active mode. It is the power-down mode that consumes the least power.
A known method of conserving power in an electrical system is by effectuating a power-down mode during which the internal clock signals that sequence the functional blocks within the electrical system are disabled. Also well known to those skilled in the art is the method of disabling, during the power-down mode, the oscillator or clock generator circuit from which the internal clock signals are derived. Without an active clock signal, the functional blocks are disabled and power consumption is minimized.
Entry into power-down mode may be under software control. Selection of the power-down mode by a software program causes a system controller to begin an internal countdown of a predetermined number of system clock cycles after which the oscillator or clock generator circuit is disabled. This countdown period may be used by the microprocessor to prepare for power-down mode before the clock is stopped. The countdown is generally accomplished by activating an internal counter. For example, a countdown of 256 clock cycles may be performed by an eight-bit counter. This countdown may be canceled if an interrupt occurs during the countdown period.
The power-down mode may be exited by the effectuation of a number of conditions such as, for example, a hardware reset or other type of interrupt.
Although the power-down mode is an effective means of conserving power, it has heretofore had a number of shortcomings and deficiencies. One of these deficiencies is the expense associated with the use of a counter to provide the delay from a request to enter power-down mode to the disablement of the oscillator.
Another shortcoming and deficiency of the use of power-down mode to conserve power is the possibility of errors caused by unstable clock pulses generated when the oscillator is first turned on.
Also, as the entry into power-down mode may be software controlled, there has been encountered problems heretofore where software error or noise results in the accidental entry of the device into the power-down mode resulting in the inadvertent disabling of most functional blocks.
Another problem associated with the use of the power-down mode is the possibility of a premature entry into the power-down mode which results in insufficient time to complete necessary housekeeping operations. This premature entry may be caused by a previous request to enter power-down mode from a different software routine.
Still another problem encountered is the possibility of the device entering the power-down mode without any means to exit the power-down mode and return to an active power mode. Such a possibility may exist, for example, when the program, prior to entry into power-down mode, fails to enable the interrupts that would signal the processor to exit the power-down mode.